The new generation high-speed cable interface technology of MCIO
With the exponential growth of artificial intelligence, high-performance computing, and the demand for massive storage, the bottleneck of data transmission has shifted from within the chip to the physical interconnection level. Over the past two decades, the PCIe bus has established its core position as the connection between CPUs, GPUs, and various accelerators and storage devices, thanks to its speed doubling with each generation - from 2.5 GT/s in PCIe 1.0 to 64 GT/s in PCIe 6.0. Meanwhile, the rise of solid-state storage has led to the rapid replacement of SATA and SAS interfaces, which require bridge conversion, by the NVMe architecture that directly connects to the CPU, achieving lower latency and higher bandwidth. However, as signal rates enter the ultra-high frequency range of PCIe 5.0/6.0, the physical losses of traditional PCB materials and cables have become a key limitation, driving the comprehensive application of complex signal integrity compensation techniques such as pre-emphasis, equalization, and amplitude adjustment at both the sending and receiving ends. To address the dual challenges of high-density interconnection and ultra-high-speed transmission at the system level, a new physical layer interface standard, MCIO, has emerged. It is not a new data protocol but an optimized high-density connection solution for carrying high-speed PCIe signals. By merging multiple PCIe channels into a single, reliable data stream through compact connectors and high-performance cables, it significantly improves signal transmission quality and system layout flexibility. This trend is accelerating in the industry: domestic server manufacturers like Inspur are vigorously promoting the application of MCIO in high-end data centers to meet the high-density interconnection requirements of multiple accelerator cards and NVMe hard drives within servers. Meanwhile, in the consumer high-end platform, such as the upcoming TRX50 WS workstation motherboard from ASRock, it is equipped with both the future-oriented PCIe 5.0 x4 MCIO interface and the Slim-SAS interface that caters to the existing ecosystem, fully unleashing the expansion potential of up to 88 PCIe lanes and demonstrating the penetration path of the new generation of interconnection technology from the cloud to the edge. Looking ahead, as new-generation interconnection protocols based on the PCIe physical layer, such as CXL, mature, high-performance and high-density physical interfaces like MCIO will become the core infrastructure supporting advanced architectures such as memory pooling and heterogeneous computing, continuously driving the entire computing industry towards higher bandwidth, lower latency, and stronger resource elasticity at the invisible hardware level.
The rear PCIe switch board of the ASRock HGX H200 server, with a large number of MCIO cables connected to the PCIe switch board - in this picture alone, there are 16 MCIO cables arranged, collectively providing 128 PCIe Gen5 lanes.
The Emergence of MCIO Interface
Before the advent of the MCIO (Multi-Channel I/O, a high-density connector system that complies with the SFF-TA-1016 standard) as a new physical interface standard, high-speed interconnection within GPU servers mainly relied on two traditional methods: either directly mounting GPUs on the motherboard through standard PCIe slots, or establishing dedicated high-speed channels between multiple GPUs via independent NVLink hard bridge devices. However, with the explosive growth in the demand for computing density and bandwidth from AI/HPC workloads, both of these methods have revealed significant bottlenecks: the PCIe card form factor severely occupies the front space of the motherboard, limiting the number of GPU deployments and thermal design; NVLink bridges and traditional high-speed cables like SFF-8644/8654 are hard and thick, making routing difficult in dense servers, affecting airflow and reducing maintainability. To systematically address these challenges, MCIO was born. It is not a new data protocol but rather a physical layer interface revolution optimized for carrying ultra-high-performance links such as PCIe 5.0/6.0, CXL, and UCIe. In GPU servers, MCIO acts as a "non-slot PCIe interface", connecting key components such as GPUs, NVLink switch modules, and high-speed network cards to the motherboard or expansion backplane through high-density, low-profile connectors and flexible high-speed cables. Its core value lies in achieving high-bandwidth, low-loss signal transmission and a compact, flexible mechanical layout, thereby completely breaking free from the spatial and wiring constraints of traditional slots, allowing GPUs to be deployed in a modular and hot-swappable manner, and enabling neat centralized interconnection and power supply through the backplane. This transformation marks the official transition of GPU interconnection from the "external expansion card" model to the new era of "modular computing resource pools", laying a solid physical foundation for the next generation of ultra-high-density, easy-to-maintain, and liquid-cooling-friendly AI servers and data center architectures. MCIO interfaces come in various types, with MCIO 4I and MCIO 8I being the most common. MCIO 4I combines four physical channels into a single high-speed data stream, enabling parallel data transmission and effectively enhancing data transmission efficiency and real-time performance. It supports multiple data transmission protocols, such as PCIe and CXL, to meet the needs of different devices and applications. MCIO 4I has been widely applied in servers, data centers, and other facilities, providing strong support for the stable operation of high-performance computing and data centers. Compared to MCIO 4I, MCIO 8I combines eight physical channels into a single high-speed data stream, further increasing the data transmission rate and throughput. It offers higher bandwidth and lower latency, meeting more demanding data transmission requirements. MCIO 8I is mainly used in scenarios that require higher data transmission rates and greater throughput, such as supercomputing and cloud computing. At this stage, MCIO can be said to be an appropriate data interface that emerged at the right time. Under the premise that its technical performance is not an issue, it should have a promising development prospect.
In the current era of explosive growth in AI and high-performance computing workloads, the soaring power consumption, rapid increase in the number of GPUs, and the sharp rise in interconnection complexity are causing traditional deployment models based on PCIe slots to encounter comprehensive bottlenecks: in terms of space, standard PCIe cards occupy a large amount of valuable area on the motherboard, limiting the density of multi-GPU deployment and cooling design; in terms of wiring, traditional SFF-8644/8654 and other high-speed cables are hard and large in size, making it difficult to flexibly route them within the dense server, seriously hindering airflow and cooling efficiency; in terms of maintainability, replacing or upgrading GPUs often requires disassembling the entire system, significantly increasing operational complexity and downtime; in terms of electrical, when providing more than 75W of power, PCIe interfaces rely on external power supply, and when transmitting ultra-high-speed signals such as PCIe 5.0/6.0, they face severe signal integrity challenges. These systemic bottlenecks are driving GPUs to accelerate their evolution from "card-based peripherals" to "modular computing units", specifically manifested as: in terms of form, adopting integrated module designs such as SXM or OAM to achieve vertical insertion and high-density deployment; in terms of interconnection, combining dedicated high-speed interconnection NVLink with the new generation of flexible high-speed cables, and completely eliminating the clutter of front-end cables through backplane interconnection; in terms of power supply, shifting to a 12V/48V backplane direct supply architecture to replace the complex external power supply cables; in terms of maintenance, developing towards hot-swappable and fully modular designs. The essence of this series of changes is to elevate GPUs to a core computing resource pool, driving AI servers to fully evolve from general-purpose computing platforms to highly integrated, efficient cooling, and flexible expandable supercomputing architectures.
Post time: May-15-2026
